Senior FPGA Design and Verification Engineer

A specialised hardware programme is developing a high performance processing platform where timing margins and verification quality are central to the design. The consultant will work between digital architecture and verification, taking responsibility for difficult logic blocks and helping the wider team reason about behaviour at both simulation and hardware level.

• Design and verify complex FPGA logic for performance sensitive applications.
• Translate architectural requirements into synthesizable and testable digital designs.
• Analyse timing closure issues and optimise critical paths.
• Develop verification environments and investigate failures across simulation and hardware.
• Participate in architecture reviews and contribute to design standards.

• 8+ years of FPGA development experience.
• Strong Verilog or VHDL skills with substantial production hardware experience.
• Experience with timing closure, synthesis and hardware debugging.
• Strong understanding of digital design and verification methodologies.
• Experience with high speed interfaces is an advantage.